Prof. PAN Quan’s main research interests are high-speed analog/RF IC designs, which include Wireline/Wireless high-speed communication ICs (both receiver and transmitter), Serdes/clock and recovery (CDR) circuits, LNA/frequency synthesizer, GaN IC, Si-Photonics. He has published multiple high-quality journals/conference papers, and he has more than 8-year industry experience, including 4-year state-of-the-art industry experience in Silicon Valley IC startup.

Working Experience

2011-Presen Associate Professor, Southern University of Science and Technology

2014-2018Senior Staff Engineer, eTopus Technology Inc. (Silicon Valley VC-backed high-speed IC Startup)

Education Background

2014D.  Department of Electrical and Computer Engineering, the Hong Kong University of Science and Technology

2005S.    Department of Electrical Engineering, University of Science and Technology of China

Major Recognition

Outstanding Young Author Award, IEEE Circuits and Systems Society, 2017.

Innovation Prize Winner, the 4th Annual HKUST One Million Dollar Entrepreneurship Competition, 2014.

Research Areas

Optical communication integrated circuits

Silicon Photonic Interconnects

Serdes/CDR

Analog/RF integrated circuits

Honors & Awards

Outstanding Young Author Award, IEEE Circuits and Systems Society, 2017.

Innovation Prize Winner, the 4th Annual HKUST One Million Dollar Entrepreneurship Competition, 2014.

Selected Publications

1. Wang, Q. Pan* et al., "A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40nm-CMOS," TCAS-II, DOI 10.1109/TCSII.2019.2925363, Jun. 2019.

2. Q. Panet al., “A 42-dBΩ 25-Gb/s CMOS Transimpedance Amplifier with Multiple-Peaking Scheme for Optical Communications,” IEEE Transactions on Circuits and Systems II: Express Briefs, Feb. 2019.

3. Guo, and Q. Pan, “A PAM-4 80-Gb/S Variable-Gain Transimpedance Amplifier in 40-nm CMOS Technology,” in IEEE International Conference on Integrated Circuits, Technologies and Applications, Nov. 2018.

4. Pan, Y. Wang, Z. Hou, L. Sun, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 41-mW 30-Gb/s CMOS Optical Receiver with Digitally-Tunable Cascaded Equalization,” in Proc. European Solid-State Circuits Conf., Sep. 2014.

5. Pan, Z. Hou, Y. Wang, Y. Lu, W. H. Ki, K. C. Wang, and C. P. Yue, “A 48-mW 18-Gb/s Fully Integrated CMOS Optical Receiver with Photodetector and Adaptive Equalizer,” inSymp. VLSI Circuits Dig. Tech. Papers, pp. 116−117, Jun. 2014.

6. Pan, Z. Hou, Y. Li, A. W. Poon, and C. P. Yue, “A 0.5-V P-Well/Deep N-Well photodetector in 65-nm CMOS for monolithic 850-nm optical receivers,” IEEE Photonics Technology Letters (PTL), vol. 26, no. 12, pp. 1184−1187, Jun. 2014.

7. Pan, T. J. Yeh, C. Jou, F. L. Hsueh, H. Luong, and C. P. Yue, “A performance study of layout and Vt options for low noise amplifier design in 65-nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symp., pp. 535−538, Jun. 2012.

8. Zhu, Q. Pan, J. Zhuang, C. Zhi, and C. P. Yue, “A Low-Power PAM4 Receiver Using 1/4-Rate Sampling Decoder with Adaptive Variable-Gain Rectification,” in 2017 IEEE Asian Solid-State Circuits Conf., Nov. 2017.

9. Wang, D. Luo, Q. Pan, L. Jing, Z. Li, and C. P. Yue, “A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator,” IEEE Transactions of Circuits and Systems−I(TCAS-I), vol. 64, issue. 3, pp. 653−663, Mar. 2017.

10. Sun, Q. Pan, K. C. Wang, and C. P. Yue, “A 26-28-Gb/s clock and data recovery circuit with embedded equalizer in 65-nm CMOS,” IEEE Transactions of Circuits and Systems−I(TCAS-I), vol. 61, no. 7, pp. 2139−2149, Jul. 2014.