Junmin Jiang (S’09-M’18) received the B.Eng. degree in Electronic and Information Engineering from Zhejiang University, Hangzhou, China, in 2011, and the Ph.D. degree in Electronic and Computer Engineering from The Hong Kong University of Science and Technology (HKUST), Hong Kong, in 2017.

He was a Visiting Scholar with the State Key Laboratory of AMSV, University of Macau, Macau, in 2015, and was a Post-Doctoral Fellow with HKUST, in 2017. He was an Analog Design Engineer with Kilby Labs Silicon Valley, Texas Instruments, Santa Clara, CA, USA, from 2018 to 2021. In 2021, he joined the Southern University of Science and Technology (SUSTech), Shenzhen, China, as an Assistant Professor. His current research interests include power management IC design, especially in switched-capacitor power converter design.

Dr. Jiang is serving as a session chair of ISCAS 2021 and on the review committee of ISCAS 2021 and 2022. He served as an Associate Editor and Guest Editor (ISCAS2022 and ISICAS2022) of IEEE Transactions of Circuits and Systems II: Express Briefs.

He was recipients of the IEEE Solid-State Circuits Society (SSCS) Student Travel Grant Award 2015, the Analog Devices Inc. (ADI) Outstanding Student Designer Award in 2015, the IEEE Solid-State Circuits Society (SSCS) Pre-Doctoral Achievement Award 2016–2017, and the ASP-DAC University LSI Design Contest Special Feature Award in 2018.